1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a non-volatile memory device including a memory cell array for 2-bit operation and a method of fabricating the same.
2. Description of the Related Art
A significant increase in memory density of non-volatile memory devices or flash memory devices is needed. Therefore, there have been efforts to reduce the size of the memory cell. There have also been introduced methods of increasing the memory density by increasing the number of states that can be stored in the memory cell. For example, a method of realizing 2-bit operation in one memory transistor structure is proposed.
FIG. 1 is a sectional view schematically illustrating a conventional non-volatile memory transistor device.
Referring to FIG. 1, a memory cell of the conventional non-volatile memory transistor device typically employs a transistor structure, which includes two source/drain regions 41, 45 in a semiconductor substrate 10, a channel 11 disposed in the substrate between the first source/drain region 41 and the second source/drain region 45, and a gate 30 formed on the channel 11. Further, a charge storage layer 20 may be interposed between the gate 30 and the semiconductor substrate 10.
It is reported that 2-bit operation is possible in the transistor structure as described above. For example, portions of the charge storage layer 20 respectively disposed close to the first and second source/drain regions 41, 45 are defined as local first and second charge storage regions 21, 23 respectively, or a storage node to realize 2-bit operation.
In order to realize 2-bit operation in such a transistor structure, first and second bit lines BL1, BL2 must be independently connected to the first and second source/drain regions 41, 45 respectively, and a word line WL must be connected to the gate 30. However, it has been understood that it is very difficult to realize an interconnection structure, in which three discrete terminals, that is, WL, BL1, BL2, are independently connected in one memory cell transistor as above.
In order to realize high integration of a memory device, several memory cells are connected to one word line WL, one bit line BL1, and one bit line BL2, and discrete memory cells must be aligned sufficiently to perform a write and/or a read operation independently. Since the bit lines BL1 and BL2 must be connected to one memory cell independently, the array of the word line WL, and the bit lines BL1 and BL2 must be considered very carefully.
If the gate 30 used for the word line WL extends along the direction that the active region extends, that is, the direction that the active region extends from the first source/drain region 41 to the second source/drain region 45, it is difficult that the bit lines BL1 and BL2 are directly connected to the first and second source/drain regions 41, 45 since the gate 30 and the charge storage layer 20 extend on the first and second source/drain regions 41, 45. Therefore, efforts have been made to design arrays of WL and BL1, BL2 for connecting memory cells for 2-bit operation.
For example, in order to realize the array structure, there has been proposed a structure extending in a direction where source/drain regions 41, 45 cross with WL, for example, a buried bit line structure. Further, there has been also proposed a structure in which a gate 30 does not extend to other neighboring memory cells and is cut, and an additional WL is connected to a discrete gate in each memory cell.
As shown in FIG. 1, if the gate 30 extends to a direction where an active region extends, that is, from a first source/drain region 41 to a second source/drain region 45, a charge storage layer 20 below the gate 30 extends together with the gate 30. In this case, the charge storage layer 20 necessarily extends to the isolation region for isolating memory cells.
The case considers convenience of processes, but may cause influences between signals of the storage charges between cells connected to one WL. Specifically, in the case that an integration density of a device for a highly-integrated memory device is increased, the mutual influence, for example, cross-talking phenomenon may be more serious. The stored charges, that is, interference between signals may function as a factor to limit the increase of integration degrees of a device. Thus, it is required to develop a process technology being capable of locally confining the charge storage layer 20.